Image processing circuit and image processing method

ABSTRACT

An image processing circuit and an image processing method are provided. The image processing circuit comprises a full search engine and a frame rate conversion (FRC) engine. The full search engine executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to the reference image and the current image. The FRC engine analyzes a scene characteristic from the current image according to SAD distribution. The FRC engine adjusts at least one of the control parameters according to the scene characteristic. The FRC engine generates an interpolated image according to the reference image, the current image and the control parameters.

This application claims the benefit of Taiwan application Serial No. 101114235, filed Apr. 20, 2012, the subject matter of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates in general to an image processing circuit and an image processing method, and more particularly to an image processing circuit using frame rate conversion (FRC) and an image processing method using the same.

2. Description of the Related Art

According to frame rate conversion (FRC), a compensation image is obtained by way of interpolation through motion estimate and motion compensation (MEMC). To obtain a correct compensation image, a correct the motion vector is firstly estimated, and then a correct compensation image is obtained according to the motion vector.

However, when calculating the motion vector, conventional frame rate conversion normally cannot obtain the overall state of the current image. Therefore, for fast-moving images or images with dramatic changes, correct compensation images cannot be obtained through correct prediction.

SUMMARY OF THE INVENTION

The invention is directed to an image processing circuit and an image processing method.

According to one embodiment of the present invention, an image processing circuit is provided. The image processing circuit comprises a full search engine and a frame rate conversion (FRC) engine. The full search engine executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to the reference image and the current image, wherein the SAD distribution comprises a plurality of sums of absolute differences. The FRC engine generates an interpolated image according to the reference image, the current image and the control parameters. When partial of the sums of absolute differences is smaller than the smallest threshold, the FRC engine determines whether the number of sums of absolute differences larger than the smallest threshold is equal to 1. When the number of sums of absolute differences is equal to 1, the current image comprises the good scene. When the number of sums of absolute differences is larger than 1, the current image comprises the periodic scene. When the sum of absolute differences is not smaller than the smallest threshold, the FRC engine determines whether sum of absolute differences is larger than an average pixel level (APL). When the sum of absolute differences is larger than the APL, the current image comprises the flash scene. When the sum of absolute differences is not larger than the APL, the current image comprises the bad scene. The FRC engine adjusts at least one of the control parameters according to the good scene, the periodic scene, the flash scene or the bad scene.

According to another embodiment of the present invention, an image processing circuit is provided. The image processing circuit comprises a full search engine and a frame rate conversion (FRC) engine. The full search engine executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to the reference image and the current image. The FRC engine generates an interpolated image according to the reference image, the current image and the control parameters, and adjusts the three-dimensional recursive search (3DRS) update vector, the SAD coring or the quantity of candidate motion vectors according to the SAD distribution.

According to an alternate embodiment of the present invention, an image processing method is provided. The image processing method comprises: executing a full search to generate a sum of sum of absolute difference (SAD) distribution according to the reference image and the current image, wherein the SAD distribution comprises a plurality of sums of absolute differences; analyzing a scene characteristic from the current image according to the SAD distribution; adjusting at least one of the control parameters according to the scene characteristic; generating an interpolated image according to the reference image, the current image and the control parameters.

The above and other aspects of the invention will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment(s). The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic diagram of an image processing circuit according to an embodiment;

FIG. 2 shows an image processing method according to an embodiment;

FIG. 3 shows a schematic diagram of a full search; and

FIG. 4 shows a detailed flowchart of step 22.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, FIG. 2 and FIG. 3 at the same time. FIG. 1 shows a schematic diagram of an image processing circuit according to an embodiment. FIG. 2 shows an image processing method according to an embodiment. FIG. 3 shows a schematic diagram of a full search. The image processing circuit 1 comprises a full search engine 11 and a frame rate conversion (FRC) engine 12. Frame rate conversion is also referred as motion estimate and motion compensation (MEMC). The image processing method can be applied in the image processing circuit 1, and at least comprises steps 21˜24.

Firstly, the method begins at step 21, the full search engine 11 executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to the reference image F(k−1) and the current image F(k), wherein the SAD distribution comprises a plurality of sums of absolute differences. In the full search, the reference image F(k−1) and the current image F(k) are divided into identical blocks. Suppose the block X illustrated in FIG. 3 is a to-be-compared block, and the search region Bx is a search region of the reference image F(k−1) to be compared with the block X. The set S denotes a set consisting of all possible motion vectors, and any motion vector s belongs to the set S, that is, sεS. The full search engine 11 searches all blocks within the search region Bx to locate a block most similar to the block X. The full search engine 11 locates the block most similar to the block X through the sums of absolute differences (SAD) expressed as:

${{SAD}\left( {{x},{y}} \right)} = \left. {\sum\limits_{m = x}^{x + N - 1}\; \sum\limits_{n = y}^{y + N - 1}}\; \middle| {{I_{k}\left( {m,n} \right)} - {I_{k - 1}\left( {{m + {x}},{n + {y}}} \right)}} \middle| . \right.$

Wherein, I_(k)(m,n) denotes the values of the pixel at the m^(th) row and the n^(th) column in the block X of the current image F(k); I_(k-1)(m+dx,n+dy) denotes the values of the pixel at the (m+dx)^(th) row and the (n+dy)^(th) column in the search region Bx.

Next, the method proceeds to step 22, the FRC engine 12 according to SAD distribution analyzes a scene characteristic from the current image F(k). Then, the method proceeds to step 23, the FRC engine 12 adjusts at least one of the control parameters according to the scene characteristic. Then, the method proceeds to step 24, the FRC engine 12 generates an interpolated image according to the reference image F(k−1), the current image F(K) and the control parameters.

Referring to FIG. 1, FIG. 3 and FIG. 4 at the same time. FIG. 4 shows a detailed flowchart of step 22. The step 22 further comprises steps 221˜227. As indicated in step 221, the FRC engine 12 determines whether partial of the sums of absolute differences is smaller than a smallest threshold. When partial of the sums of absolute differences is smaller than the smallest threshold, this indicates that a block similar to the block X is found in the search region Bx, and step 222 is executed accordingly. As indicated in step 222, the FRC engine 12 further determines whether the number of sums of absolute differences larger than the smallest threshold is equal to 1.

When the number of sums of absolute differences is equal to 1, the method proceeds to step 223, the FRC engine 12 analyzes that the current image F(k) comprises a good scene. Conversely, when is larger than the smallest threshold the number of sums of absolute differences is larger than 1, the method proceeds to step 224, the FRC engine 12 analyzes that the current image F(k) comprises a periodic scene.

When all of the sums of absolute differences is not smaller than the smallest threshold, the method proceeds to step 225, the FRC engine 12 further determines whether all of the sums of absolute differences is larger than an average pixel level (APL). When all of the sums of absolute differences is larger than the APL, the method proceeds to step 226, the FRC engine 12 analyzes that the current image F(k) comprises a flash scene. Conversely, when all of the sums of absolute differences is not larger than the APL, the method proceeds to step 227, the FRC engine 12 analyzes that the current image F(k) comprises a bad scene.

The said control parameters such as comprises an update vector used in a three-dimensional recursive search (3DRS), a SAD coring (SAD coring) or a quantity of candidate motion vectors. The reference vector for the i^(tb) calculation of a block is expressed as:

${c_{i} = \begin{Bmatrix} {d\left( {{x + p_{i}},k} \right)} \\ {d\left( {{x + p},{k - 1}} \right)} \\ {{c_{j} + u},{j \neq i},{u \in {US}}} \end{Bmatrix}},$

wherein c_(i)=d(x+p_(i),k) denotes a space reference; p_(i) denotes a relative position; k denotes an k^(th) image; c_(i)=d(x+p_(i),k−1) denotes a time reference; k−1 denotes a (k−1)^(th) image. The vector in a search region is expressed as: c_(i)=c_(j)+u, j≠i,uεUS. The update vector u is selected from an update set US. Therefore, when the update vector u increases, this indicates that update rate will increase. Conversely, when the update vector u decreases, this indicates that update rate will decrease.

When the current image comprises the good scene, the FRC engine 12 keeps the update vector u unchanged. When the current image comprises the periodic scene or the flash scene, the FRC engine 12 decreases the update vector u to decrease update rate. Conversely, when the current image comprises the bad scene, the FRC engine 12 increases the update vector u to speed up update rate.

Likewise, the said FRC engine 12 may adjust the quantity of candidate motion vectors according to the scene characteristic. For example, when the current image comprises the good scene, the FRC engine 12 keeps the quantity of candidate motion vectors unchanged. When the current image comprises the periodic scene, the flash scene or the bad scene, the FRC engine 12 decreases the quantity of candidate motion vectors.

In addition, to make the motion vector more smoothed, the sum of absolute differences is deducted by a SAD coring, so as to increase the likelihood of finding the same motion vector. The said FRC engine 12 may adjust the SAD coring according to the scene characteristic. For example, when the current image comprises the good scene, the FRC engine 12 keeps the SAD coring unchanged. When the current image comprises the flash scene, the FRC engine 12 decreases the SAD coring. Conversely, when the current image comprises the periodic scene, or the bad scene, the FRC engine 12 increases the SAD coring.

While the invention has been described by way of example and in terms of the preferred embodiment(s), it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures. 

What is claimed is:
 1. An image processing circuit, comprising: a full search engine, which executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to a reference image and a current image, wherein the SAD distribution comprises a plurality of sums of absolute differences; and a frame rate conversion (FRC) engine, which generates an interpolated image according to the reference image, the current image and a plurality of the control parameters, wherein the FRC engine determines whether the number of sums of absolute differences larger than the smallest threshold is equal to 1 when partial of the sums of absolute differences is smaller than the smallest threshold, the current image comprises a good scene when the number of sums of absolute differences is equal to 1, the current image comprises a periodic scene when the number of sums of absolute differences is larger than 1, the FRC engine determines whether the sum of absolute differences is larger than an average pixel level (APL) when the sum of absolute differences is not smaller than the smallest threshold, the current image comprises a flash scene when the sum of absolute differences is larger than the APL, the current image comprises a bad scene when the sum of absolute differences is not larger than the APL, and the FRC engine adjusts the at least one of the control parameters according to the good scene, the periodic scene, the flash scene or the bad scene.
 2. The image processing circuit according to claim 1, wherein the control parameters comprises an update vector used in a three-dimensional recursive search (3DRS).
 3. The image processing circuit according to claim 2, wherein the frame rate converter increases the update vector when the current image comprises the bad scene and decreases the update vector when the current image comprises the flash scene or the periodic scene.
 4. The image processing circuit according to claim 1, wherein the control parameters comprise a SAD coring (SAD coring).
 5. The image processing circuit according to claim 4, wherein the frame rate converter increases the update vector when the current image comprises the bad scene or the periodic scene, and decreases the update vector when the current image comprises a flash scene.
 6. The image processing circuit according to claim 1, wherein the control parameters comprise a quantity of candidate motion vectors.
 7. The image processing circuit according to claim 6, wherein the frame rate converter decreases the update vector when the current image comprises the bad scene, the flash scene or the periodic scene.
 8. An image processing circuit, comprising: a full search engine, which executes a full search to generate a sum of sum of absolute difference (SAD) distribution according to a reference image and a current image; and a frame rate conversion (FRC) engine, which generates an interpolated image according to the reference image, the current image and a plurality of the control parameters, and adjusts an update vector used in a three-dimensional recursive search (3DRS), a SAD coring or a quantity of candidate motion vectors according to the SAD distribution.
 9. The image processing circuit according to claim 8, wherein the FRC engine determines whether the number of sums of absolute differences larger than the smallest threshold is equal to 1 when partial of the sums of absolute differences is smaller than the smallest threshold, the current image comprises a good scene when the number of sums of absolute differences is equal to 1, and the current image comprises a periodic scene when the number of sums of absolute differences is larger than
 1. 10. The image processing circuit according to claim 9, wherein the frame rate converter decreases the update vector when the current image comprises the periodic scene.
 11. The image processing circuit according to claim 9, wherein the frame rate converter increases the SAD coring when the current image comprises the periodic scene.
 12. The image processing circuit according to claim 9, wherein the frame rate converter decreases the quantity of candidate motion vectors when the current image comprises the periodic scene.
 13. The image processing circuit according to claim 8, wherein the FRC engine determines whether the sum of absolute differences is larger than an average pixel level (APL) when the sum of absolute differences is not smaller than the smallest threshold, and the current image comprises a flash scene when the sum of absolute differences is larger than the APL.
 14. The image processing circuit according to claim 13, wherein the frame rate converter decreases the update vector when the current image comprises the flash scene.
 15. The image processing circuit according to claim 13, wherein the frame rate converter decreases the SAD coring when the current image comprises the flash scene.
 16. The image processing circuit according to claim 13, wherein the frame rate converter decreases the quantity of candidate motion vectors when the current image comprises the flash scene.
 17. The image processing circuit according to claim 8, wherein the FRC engine determines whether the sum of absolute differences is larger than an average pixel level (APL) when the sum of absolute differences is not smaller than the smallest threshold, and the FRC engine determines the current image comprises a bad scene when the sum of absolute differences is not larger than the APL.
 18. The image processing circuit according to claim 17, wherein the frame rate converter increases the update vector when the current image comprises the bad scene.
 19. The image processing circuit according to claim 17, wherein the frame rate converter increases the SAD coring when the current image comprises the bad scene.
 20. The image processing circuit according to claim 17, wherein the frame rate converter decreases the quantity of candidate motion vectors when the current image comprises the flash scene.
 21. An image processing method, comprising: executing a full search to generate a sum of sum of absolute difference (SAD) distribution according to a reference image and a current image, wherein the SAD distribution comprises a plurality of sums of absolute differences; analyzing a scene characteristic from the current image according to the SAD distribution; adjusting at least one of the control parameters according to the scene characteristic; and generating an interpolated image according to the reference image, the current image and the control parameters.
 22. The image processing method according to claim 21, wherein the analyzing step comprises: determining whether partial of the sums of absolute differences is smaller than a smallest threshold; determining whether the number of sums of absolute differences larger than the smallest threshold is equal to 1 when partial of the sums of absolute differences is smaller than the smallest threshold; determining that the current image comprises a good scene when the number of sums of absolute differences is equal to 1; determining that the current image comprises a periodic scene when the number of sums of absolute differences is larger than 1; determining whether the sum of absolute differences is larger than an average pixel level (APL) when the sum of absolute differences is not smaller than the smallest threshold; determining that the current image comprises a flash scene when the sum of absolute differences is larger than the APL; and determining that the current image comprises a bad scene when the sum of absolute differences is not larger than the APL.
 23. The image processing method according to claim 21, wherein the control parameters comprise an update vector used in a three-dimensional recursive search (3DRS), and the update vector is decreased when the current image comprises a periodic scene.
 24. The image processing method according to claim 21, wherein the control parameters comprises a SAD coring, and the SAD coring is increased when the current image comprises a periodic scene.
 25. The image processing method according to claim 21, wherein the control parameters comprises a quantity of candidate motion vectors, and the quantity of candidate motion vectors is decreased when the current image comprises a periodic scene.
 26. The image processing method according to claim 21, wherein the control parameters comprises an update vector used in a three-dimensional recursive search (3DRS), and the update vector is decreased when the current image comprises a flash scene.
 27. The image processing method according to claim 21, wherein the control parameters comprises a SAD coring, and the SAD coring is decreased when the current image comprises a flash scene.
 28. The image processing method according to claim 21, wherein the control parameters comprises a quantity of candidate motion vectors, and the quantity of candidate motion vectors is decreased when the current image comprises a flash scene.
 29. The image processing method according to claim 21, wherein the control parameters comprises an update vector used in a three-dimensional recursive search (3DRS), and the update vector is increased when the current image comprises a bad scene.
 30. The image processing method according to claim 21, wherein the control parameters comprises a SAD coring, and the SAD coring is increased when the current image comprises a bad scene.
 31. The image processing method according to claim 21, wherein the control parameters comprises a quantity of candidate motion vectors, and the quantity of candidate motion vectors is decreased when the current image comprises a flash scene. 